| Created: | 18.05.2018 13:19:49 |
| Modified: | 13.06.2018 12:18:03 |
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Private vuint32_t NVIC_ISER0 |
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Private vuint32_t NVIC_ISER1 |
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Private vuint32_t NVIC_ISER2 |
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Private vuint32_t RESERVED_1 |
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Private vuint32_t NVIC_ICER0 |
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Private vuint32_t NVIC_ICER1 |
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Private vuint32_t NVIC_ICER2 |
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Private vuint32_t RESERVED_2 |
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Private vuint32_t NVIC_ISPR0 |
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Private vuint32_t NVIC_ISPR1 |
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Private vuint32_t NVIC_ISPR2 |
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Private vuint32_t RESERVED_3 |
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Private vuint32_t NVIC_ICPR0 |
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Private vuint32_t NVIC_ICPR1 |
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Private vuint32_t NVIC_ICPR2 |
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Private vuint32_t RESERVED_4 |
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Private vuint32_t NVIC_IABR0 |
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Private vuint32_t NVIC_IABR1 |
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Private vuint32_t RESERVED_5 |
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Private vuint32_t NVIC_STIR |
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| Operation | ||
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Public setNVIC_ISER0( parNVIC_ISER0: vuint32_t,
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Sequential
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Public setNVIC_ISER1( parNVIC_ISER1: vuint32_t,
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Sequential
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Public setNVIC_ISER2( parNVIC_ISER2: vuint32_t,
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Sequential
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Public setNVIC_ICER0( parNVIC_ICER0: vuint32_t,
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Sequential
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Public setNVIC_ICER1( parNVIC_ICER1: vuint32_t,
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Sequential
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Public setNVIC_ICER2( parNVIC_ICER2: vuint32_t,
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Sequential
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Public setNVIC_ISPR0( parNVIC_ISPR0: vuint32_t,
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Sequential
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Public setNVIC_ISPR1( parNVIC_ISPR1: vuint32_t,
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Sequential
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Public setNVIC_ISPR2( parNVIC_ISPR2: vuint32_t,
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Sequential
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Public setNVIC_ICPR0( parNVIC_ICPR0: vuint32_t,
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Sequential
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Public setNVIC_ICPR1( parNVIC_ICPR1: vuint32_t,
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Sequential
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Public setNVIC_ICPR2( parNVIC_ICPR2: vuint32_t,
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Sequential
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Public setNVIC_IABR0( parNVIC_IABR0: vuint32_t,
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Sequential
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Public setNVIC_IABR1( parNVIC_IABR1: vuint32_t,
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Sequential
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Public getNVIC_ISER0():vuint32_t |
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Sequential
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Public getNVIC_ISER1():vuint32_t |
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Sequential
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Public getNVIC_ISER2():vuint32_t |
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Sequential
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Public getNVIC_ICER0():vuint32_t |
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Sequential
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Public getNVIC_ICER1():vuint32_t |
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Sequential
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Public getNVIC_ICER2():vuint32_t |
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Sequential
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Public getNVIC_ISPR0():vuint32_t |
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Sequential
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Public getNVIC_ISPR1():vuint32_t |
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Sequential
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Public getNVIC_ISPR2():vuint32_t |
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Sequential
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Public getNVIC_ICPR0():vuint32_t |
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Sequential
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Public getNVIC_ICPR1():vuint32_t |
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Sequential
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Public getNVIC_ICPR2():vuint32_t |
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Sequential
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Public getNVIC_IABR0():vuint32_t |
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Sequential
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Public getNVIC_IABR1():vuint32_t |
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Sequential
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Protected STM32F10x_NVIC_Reg(): |
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Sequential
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Protected ~STM32F10x_NVIC_Reg(): |
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Sequential
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| Element | Source Role | Target Role |
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«typedef» vuint32_t Class |
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Name: NVIC_STIR |
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«typedef» vuint32_t Class |
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Name: RESERVED_4 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICER0 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISPR1 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICPR1 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISER2 |
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«typedef» vuint32_t Class |
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Name: NVIC_IABR1 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICPR2 |
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«typedef» vuint32_t Class |
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Name: RESERVED_3 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISPR0 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISER0 |
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«typedef» vuint32_t Class |
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Name: NVIC_IABR0 |
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«typedef» vuint32_t Class |
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Name: RESERVED_2 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISPR2 |
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«typedef» vuint32_t Class |
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Name: RESERVED_5 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICPR0 |
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«typedef» vuint32_t Class |
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Name: RESERVED_1 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICER2 |
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«typedef» vuint32_t Class |
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Name: NVIC_ICER1 |
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«typedef» vuint32_t Class |
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Name: NVIC_ISER1 |
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| Element | Source Role | Target Role |
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STM32F10x_NVIC Class |
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Name: ptrRegBaseAdr |
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