: Public Class
Created: 18.05.2018 13:19:50
Modified: 13.06.2018 12:19:03
Project:
Advanced:
Attribute
Private vuint32_t
  TIM_CR1
Details:
 
Private vuint32_t
  TIM_CR2
Details:
 
Private vuint32_t
  TIM_SMCR
Details:
 
Private vuint32_t
  TIM_DIER
Details:
 
Private vuint32_t
  TIM_SR
Details:
 
Private vuint32_t
  TIM_EGR
Details:
 
Private vuint32_t
  TIM_CCMR1
Details:
 
Private vuint32_t
  TIM_CCMR2
Details:
 
Private vuint32_t
  TIM_CCER
Details:
 
Private vuint32_t
  TIM_CNT
Details:
 
Private vuint32_t
  TIM_PSC
Details:
 
Private vuint32_t
  TIM_ARR
Details:
 
Private vuint32_t
  RESERVED_1
Details:
 
Private vuint32_t
  TIM_CCR1
Details:
 
Private vuint32_t
  TIM_CCR2
Details:
 
Private vuint32_t
  TIM_CCR3
Details:
 
Private vuint32_t
  TIM_CCR4
Details:
 
Private vuint32_t
  RESERVED_2
Details:
 
Private vuint32_t
  TIM_DCR
Details:
 
Private vuint32_t
  TIM_DMAR
Details:
 
Operation
Public
setTIM_CR1( parTIM_CR1: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CR2( parTIM_CR2: vuint32_t,
):void
Details:
Sequential
Public
setTIM_SMCR( parTIM_SMCR: vuint32_t,
):void
Details:
Sequential
Public
setTIM_DIER( parTIM_DIER: vuint32_t,
):void
Details:
Sequential
Public
setTIM_SR( parTIM_SR: vuint32_t,
):void
Details:
Sequential
Public
setTIM_EGR( parTIM_ERG: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCMR1( parTIM_CCMR1: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCMR2( parTIM_CCMR2: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCER( parTIM_CCER: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CNT( parTIM_CNT: vuint32_t,
):void
Details:
Sequential
Public
setTIM_PSC( parTIM_PSC: vuint32_t,
):void
Details:
Sequential
Public
setTIM_ARR( parTIM_ARR: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCR1( parTIM_CCR1: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCR2( parTIM_CCR2: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCR3( parTIM_CCR3: vuint32_t,
):void
Details:
Sequential
Public
setTIM_CCR4( parTIM_CCR4: vuint32_t,
):void
Details:
Sequential
Public
setTIM_DCR( parTIM_DCR: vuint32_t,
):void
Details:
Sequential
Public
setTIM_DMAR( parTIM_DMAR: vuint32_t,
):void
Details:
Sequential
Public
getTIM_CR1():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CR2():vuint32_t
Details:
Sequential isQuery
Public
getTIM_SMCR():vuint32_t
Details:
Sequential isQuery
Public
getTIM_DIER():vuint32_t
Details:
Sequential isQuery
Public
getTIM_SR():vuint32_t
Details:
Sequential isQuery
Public
getTIM_EGR():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCMR1():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCMR2():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCER():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CNT():vuint32_t
Details:
Sequential isQuery
Public
getTIM_PSC():vuint32_t
Details:
Sequential isQuery
Public
getTIM_ARR():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCR1():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCR2():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCR3():vuint32_t
Details:
Sequential isQuery
Public
getTIM_CCR4():vuint32_t
Details:
Sequential isQuery
Public
getTIM_DCR():vuint32_t
Details:
Sequential isQuery
Public
getTIM_DMAR():vuint32_t
Details:
Sequential isQuery
Protected
STM32F10x_TIM_Reg():
Details:
Sequential
Protected
~STM32F10x_TIM_Reg():
Details:
Sequential
Element Source Role Target Role
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_DCR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCMR1
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCR4
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCMR2
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_DMAR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCR3
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCR1
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_SMCR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: RESERVED_2
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_PSC
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CNT
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCER
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: RESERVED_1
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CR2
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_SR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_DIER
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_ARR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CCR2
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_EGR
 
Details:
 
«typedef» vuint32_t
Class  
Name:  
 
Name: TIM_CR1
 
Details:
 
Element Source Role Target Role
STM32F10x_TIM
Class  
Name:  
 
Name: ptrRegBaseAdr
 
Details: